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Final Electrical Specifications
LTC1417 Low Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O
January 1999
FEATURES
s s s s s s s s s s s s
DESCRIPTIO
Single Supply 5V or 5V Operation Sample Rate: 400ksps 1.25LSB INL and 1LSB DNL Max Power Dissipation: 20mW (Typ) Serial Data Output No Missing Codes Over Temperature Power Shutdown: Nap and Sleep External or Internal Reference Differential High Impedance Analog Input Input Range: 0V to 4.096V or 2.048V 82dB S/(N + D) and 95dB THD at Nyquist 16-Pin Narrow SSOP Package
The LTC (R)1417 is a low power, 400ksps, 14-bit A/D converter. This versatile device can operate from a single 5V or 5V supplies. An onboard high performance sample-andhold, a precision reference and internal trimming minimize external circuitry requirements. The low 20mW power dissipation is made even more attractive with two userselectable power shutdown modes. The LTC1417 converts 0V to 4.096V unipolar inputs from a single 5V supply and 2.048V bipolar inputs from 5V supplies. DC specs include 1.25LSB INL, 1LSB DNL and no missing codes over temperature. Outstanding AC performance includes 82dB S/(N + D) and 95dB THD at the Nyquist input frequency of 200kHz. The internal clock is trimmed for 2s maximum conversion time. The clock automatically synchronizes to each sample command, eliminating problems with asynchronous clock noise found in competitive devices. A separate convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATI
s s s s s
S
High Speed Data Acquisition Digital Signal Processing Isolated Data Acquisition Systems Audio and Telecom Processing Spectrum Instrumentation
TYPICAL APPLICATI
400kHz, 14-Bit Sampling A/D Converter
5V 10F VDD LTC1417 AIN+ S/H AIN
-
Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency
14 12 10 8 6 4 2 1k 10k 100k INPUT FREQUENCY (Hz) 1M
1417 TA02
14-BIT ADC
14 SERIAL PORT
EFFECTIVE BITS
4.096V REFCOMP 10F BUFFER
EXTCLKIN SCLK CLKOUT DOUT
8k VREF 1F
2.5V REFERENCE
TIMING AND LOGIC
BUSY RD CONVST SHDN
1417 TA01
AGND
VSS (0V OR - 5V)
DGND
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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86 80 74 68 62 S/(N + D) (dB)
UO
UO
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LTC1417 ABSOLUTE
(Notes 1, 2)
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RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW AIN+ AIN- VREF REFCOMP AGND EXTCLKIN SCLK CLKOUT 1 2 3 4 5 6 7 8 16 VDD 15 VSS 14 BUSY 13 CONVST 12 RD 11 SHDN 10 DGND 9 DOUT
Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS) Bipolar Operation Only .......................... - 6V to GND Total Supply Voltage (VDD to VSS) Bipolar Operation Only ....................................... 12V Analog Input Voltage (Note 3) Unipolar Operation .................. - 0.3V to (VDD + 0.3V) Bipolar Operation............ (VSS - 0.3) to (VDD + 0.3V) Digital Input Voltage (Note 4) Unipolar Operation ............................... - 0.3V to 10V Bipolar Operation.........................(VSS - 0.3V) to 10V Digital Output Voltage Unipolar Operation ................... - 0.3 to (VDD + 0.3V) Bipolar Operation........... (VSS - 0.3V) to (VDD + 0.3V) Power Dissipation ............................................. 500mW Operating Temperature Range LTC1417C............................................... 0C to 70C LTC1417I ............................................ - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1417ACGN LTC1417CGN LTC1417AIGN LTC1417IGN GN PART MARKING 1417A 1417 1417AI 1417I
GN PACKAGE 16-LEAD (NARROW) PLASTIC SSOP
TJMAX = 110C, JA = 95C/W
Consult factory for Military grade parts.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco External Reference (Note 8) Internal Reference External Reference = 2.5V (Note 7) CONDITIONS
With Internal Reference (Notes 5, 6)
MIN
q q q q
LTC1417 TYP MAX 0.8 0.7 5 10 5 15 5 2 1.5 20 60 30
MIN 14
LTC1417A TYP MAX 0.5 0.35 2 20 5 10 20 1 1.25 1 10 60 15
UNITS Bits LSB LSB LSB LSB LSB ppm/C ppm/C ppm/C
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IOUT(REF) = 0, Internal Reference, Commercial IOUT(REF) = 0, Internal Reference, Industrial IOUT(REF) = 0, External Reference
A ALOG I PUT
SYMBOL PARAMETER VIN IIN CIN
(Note 5)
CONDITIONS 4.75V VDD 5.25V (Unipolar) 4.75V VDD 5.25V, - 5.25V VSS - 4.75V (Bipolar) CONVST = High Between Conversions (Sample Mode) During Conversions (Hold Mode)
q q q
MIN
TYP 0 to 4.096 2.048
MAX
UNITS V V
Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance
1 14 3
2
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A pF pF
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LTC1417
A ALOG I PUT
SYMBOL PARAMETER tACQ tAP tjitter CMRR
Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Time Sample-and-Hold Aperture Time Jitter Analog Input Common Mode Rejection Ratio 0V < (AIN+ = AIN-) < 4.096V (Unipolar) - 2.048V < (AIN+ = AIN-) < 2.048V (Bipolar)
DY A IC ACCURACY
SYMBOL S/(N + D) THD SFDR IMD PARAMETER
Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Spurious Noise Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance CONDITIONS IOUT = 0 IOUT = 0, Commercial IOUT = 0, Industrial 4.75V VDD 5.25V - 5.25V VSS - 4.75V 0.1mA |IOUT| 0.1mA
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage High-Z Output Leakage DOUT, CLKOUT High-Z Output Capacitance DOUT, CLKOUT Output Source Current Output Sink Current VDD = 4.75V, IO = - 10A VDD = 4.75V, IO = - 200A VDD = 4.75V, IO = 160A VDD = 4.75V, IO = - 1.6mA VOUT = 0V to VDD, RD High RD High (Note 9) VOUT = 0V VOUT = VDD CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD
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WU
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(Note 5)
CONDITIONS
q
MIN
TYP 150 -1.5 5 65 65
MAX 500
UNITS ns ns psRMS dB dB
(Note 5)
CONDITIONS 100kHz Input Signal 200kHz Input Signal 100kHz Input Signal, First Five Harmonics 200kHz Input Signal, First Five Harmonics 200kHz Input Signal fIN1 = 90kHz, fIN2 = 100kHz S/(N + D) 77dB
q q q
MIN 79 - 85
TYP 82 82 - 95 - 95 95 - 90 10 0.8
MAX
UNITS dB dB dB dB dB dB MHz MHz
U
(Note 5)
MIN 2.480 TYP 2.500 10 20 0.05 0.05 8 MAX 2.520 UNITS V ppm/C ppm/C LSB/V LSB/V k
(Note 5)
MIN
q q q
TYP
MAX 0.8 10
UNITS V V A pF V V
2.4
1.4 4.74
q q q q
4.0 0.05 0.10 0.4 10 15 - 10 10
V V A pF mA mA
3
LTC1417
POWER REQUIRE E TS
SYMBOL PARAMETER VDD VSS IDD Positive Supply Voltage (Notes 10, 11) Negative Supply Voltage (Note 10) Positive Supply Current Nap Mode Sleep Mode ISS Negative Supply Current Nap Mode Sleep Mode Power Dissipation Bipolar Only (VSS = 0V for Unipolar) Unipolar, RD High (Note 5) Bipolar, RD High (Note 5) SHDN = 0V, RD = 0V SHDN = 0V, RD = 5V Bipolar, RD High (Note 5) SHDN = 0V, RD = 0V SHDN = 0V, RD = 5V Unipolar Bipolar
q q
PDIS
TI I G CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ + tCONV t1 t2 t3 t4 t5 t6 t7 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Acquisition Plus Conversion Time
SHDN to CONVST Wake-Up Time from Nap Mode CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY Delay Between Conversions Wait Time RD After BUSY Data Access Time After RD
t8 t9 t10 t11 t12 fSCLK fEXTCLKIN tdEXTCLKIN
Bus Relinquish Time RD Low Time CONVST High Time Delay Time, SCLK to DOUT Valid Time from Previous Data Remain Valid After SCLK Shift Clock Frequency External Conversion Clock Frequency Delay Time, CONVST to External Conversion Clock Input (Note 9) CL = 25pF CL = 25pF
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UW
(Note 5)
MIN 4.75 - 4.75 4.0 4.3 750 0.1 2.0 0.7 1.5 20.0 31.5 TYP MAX 5.25 - 5.25 5.5 6.0 UNITS V V mA mA A A mA A nA mW mW
CONDITIONS
q
2.8
q q
27.5 44
UW
(Note 5)
CONDITIONS
q q q q
MIN 400
TYP 1.8 150 2.1 500
MAX 2.25 500 2.5
UNITS kHz s ns s ns ns
(Note 10) (Notes 10, 11) CL = 25pF CL = 25pF (Note 10) CL = 25pF
q q q q q q
40 35 7 250 -5 15 20 30 40 40 55 35 t7 40 15 5 0 0.05 10 20 9 20 40 12 70
ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz s
CL = 100pF
q q q q q q q q q
LTC1417
TI I G CHARACTERISTICS
SYMBOL tH SCLK tL SCLK tH EXTCLKIN tL EXTCLKIN PARAMETER SCLK High Time SCLK Low Time EXTCLKIN High Time EXTCLKIN Low Time
The q indicates specifications which apply over the full operating temperature range; all other limits and typicals TA = 25C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA without latchup if the pin is driven below VSS (ground for unipolar mode) or above VDD. Note 4: When these pin voltages are taken below VSS they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = - 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless otherwise specified.
PI FU CTIO S
AIN+ (Pin 1): Positive Analog Input. AIN- (Pin 2): Negative Analog Input. VREF (Pin 3): 2.50V Reference Output. Bypass to AGND with 1F. REFCOMP (Pin 4): 4.096V Reference Output. Bypass to AGND using 10F tantalum in parallel with 0.1F ceramic. AGND (Pin 5): Analog Ground. EXTCLKIN (Pin 6): External Conversion Clock Input. A 5V input will enable the internal conversion clock. SCLK (Pin 7): Data Clock Input. CLKOUT (Pin 8): Conversion Clock Output. DOUT (Pin 9): Serial Data Output. DGND (Pin 10): Digital Ground. SHDN (Pin 11): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by RD. RD = 0 for nap mode and RD = 1 for sleep mode. RD (Pin 22): Read Input. This enables the output drivers. RD also sets the shutdown mode when SHDN goes low. RD and SHDN low selects the quick wake-up nap mode, RD high and SHDN low selects sleep mode. CONVST (Pin 13): Conversion Start Signal. This active low signal starts a conversion on its falling edge. BUSY (Pin 14): The BUSY output shows the converter status. It is low when a conversion is in progress. VSS (Pin 15): Negative Supply, -5V for Bipolar Operation. Bypass to AGND using 10F tantalum in parallel with 0.1F ceramic. Analog ground for unipolar operation. VDD (Pin 16): 5V Positive Supply. Bypass to AGND with 10F tantalum in parallel with 0.1F ceramic.
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UW U
(Note 5)
CONDITIONS
q q q q
MIN 40 40 0.04 0.04
TYP
MAX
UNITS ns ns
20 20
s s
Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN- grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best results ensure that CONVST returns high either within 625ns after conversion start or after BUSY rises.
5
LTC1417
TEST CIRCUITS
Load Circuits for Access Timing
5V 1k DOUT 1k DGND A) HI-Z TO VOH AND VOL TO VOH CL DOUT CL DGND B) HI-Z TO VOL AND VOH TO VOL
1417 TC01
Load Circuits for Output Float Delay
5V 1k DOUT 1k 30pF DOUT 30pF
A) VOH TO HI-Z
B) VOL TO HI-Z
1417 TC02
FU CTIO AL BLOCK DIAGRA
AIN+
CSAMPLE
CSAMPLE AIN- VREF 8k 2.5V REF ZEROING SWITCHES
REF AMP
14-BIT CAPACITIVE DAC
REFCOMP (4.096V) AGND DGND INTERNAL CLOCK MUX
SUCCESSIVE APPROXIMATION REGISTER
EXTCLKIN
SHDN
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VDD VSS (0V FOR UNIPOLAR MODE -5V FOR BIPOLAR MODE)
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+
COMP
-
14 SHIFT REGISTER DOUT SCLK CONTROL LOGIC
1417 BD
CONVST
RD
CLKOUT BUSY
LTC1417
APPLICATIONS INFORMATION
CONVERSION DETAILS The LTC1417 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit serial output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CONVST input. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN+ and AIN- inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 500ns will provide enough time for the sampleand-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN- input charges. The SAR contents (a 14-bit data word) which represent the difference of AIN+ and AIN- are output through the serial pin DOUT.
AIN+
SAMPLE
AIN-
SAMPLE
VDAC+
Figure 1. Simplified Block Diagram
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CSAMPLE+ HOLD CSAMPLE- HOLD CDAC+ ZEROING SWITCHES HOLD HOLD
+
CDAC
-
COMP
-
VDAC- 14 SAR SHIFT REGISTER
DOUT
1417 F01
7
LTC1417
APPLICATIONS INFORMATION
DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1417 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN- input is grounded). The AIN+ and AIN- inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1417 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 2). For minimum acquisition time, with high source impedance, a buffer amplifier must be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts -- 500ns for full throughput rate.
100
ACQUISITION TIME (s)
10
1
0.1
0.01 1 10 100 1k 10k SOURCE RESISTANCE () 100k
1417 F02
Figure 2. tACQ vs Source Resistance
Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, choose an amplifier that has a low output impedance (<100) at the closed-loop
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bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a closed-loop bandwidth of 10MHz, then the output impedance at 10MHz must be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 10MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1417 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1417. More detailed information is available in the Linear Technology Databooks and on the LinearViewTM CD-ROM. LT (R)1354: 12MHz, 400V/s Op Amp. 1.25mA maximum supply current. Good AC and DC specifications. Suitable for dual supply application. LT1357: 25MHz, 600V/s Op Amp. 2.5mA maximum supply current. Good AC and DC specifications. Suitable for dual supply application. LT1366/LT1367: Dual/Quad Precision Rail-to-Rail Input and Output Op Amps. 375A supply current per amplifier. 1.8V to 15V supplies. Low input offset voltage: 150V. Good for low power and single supply applications with sampling rates of 20ksps and under. LT1498/LT1499: 10MHz, 6V/s, Dual/Quad Rail-to-Rail Input and Output Op Amps. 1.7mA supply current per amplifier. 2.2V to 15V supplies. Good AC performance, input noise voltage = 12nV/Hz (typ). LT1630/LT1631: 30MHz, 10V/s, Dual/Quad Rail-to-Rail Input and Output Precision Op Amps. 3.5mA supply current per amplifier. 2.7V to 15V supplies. Best AC performance, input noise voltage = 6nV/Hz (typ), THD = - 86dB at 100kHz.
LinearView is a trademark of Linear Technology Corporation.
LTC1417
APPLICATIONS INFORMATION
Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1417 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 10MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 3 shows a 2000pF capacitor from + AIN to ground and a 100 source resistor to limit the input bandwidth to 800kHz. The 2000pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Input Range The 2.048V and 0V to 4.096V input ranges of the LTC1417 are optimized for low noise and low distortion. Most op amps also perform well over these ranges, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1417 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range.
ANALOG INPUT 2000pF
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1 2 3 4 10F 5
AIN+ AIN- VREF LTC1417
REFCOMP AGND
1417 F03
Figure 3. RC Input Filter
9
LTC1417
APPLICATIONS INFORMATION
INTERNAL REFERENCE The LTC1417 has an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 2.500V. It is internally connected to a reference amplifier and is available at Pin 3. A 8k resistor is in series with the output so that it can be easily overdriven in applications where an external reference is required, see Figure 4. The reference amplifier compensation pin (REFCOMP, Pin 4) must be connected to a capacitor to ground. The reference is stable with capacitors of 1F or greater. For the best noise performance, a 10F in parallel with a 0.1F ceramic is recommended. The VREF pin can be driven with a DAC or other means to provide input span adjustment. The reference should be kept in the range of 2.25V to 2.75V for specified linearity. UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT Figure 5a shows the ideal input/output characteristics for the LTC1417. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, ... FS - 1.5LSB). The output code is natural binary with 1LSB = FS/16384 = 4.096V/16384 = 250V. Figure 5b shows the input/output transfer characteristics for the bipolar mode in two's complement format.
5V VIN VOUT LT1460 10F
Figure 4. Using the LT1460 as an External Reference
111...111 111...110 111...101
OUTPUT CODE
1LSB =
FS = 4.096V 16384 16384
OUTPUT CODE
111...100
000...011 000...010 000...001 000...000 0V
UNIPOLAR ZERO
1 LSB INPUT VOLTAGE (V)
FS - 1LSB
1417 F05a
Figure 5a. LTC1417 Unipolar Transfer Characteristics
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5V 1 ANALOG INPUT 2 3 4 0.1F 5 VDD
AIN+ AIN- VREF
LTC1417
REFCOMP AGND
1417 F04
011...111 011...110 BIPOLAR ZERO
000...001 000...000 111...111 111...110
100...001 100...000 -FS/2
FS = 4.096V 1LSB = FS/16384 -1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 - 1LSB
1417 F05b
Figure 5b. LTC1417 Bipolar Transfer Characteristics
LTC1417
APPLICATIONS INFORMATION
Unipolar Offset and Full-Scale Error Adjustment In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figures 6a and 6b show the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN- input. For zero offset error apply 125V (i.e., 0.5LSB) at the input and adjust the offset at the AIN- input until the output code flickers between 0000 0000 0000 00 and 0000 0000 0000 01. For full-scale adjustment, an input voltage of 4.095625V (FS - 1.5LSBs) is applied to AIN+ and R2 is adjusted until the output code flickers between 1111 1111 1111 10 and 1111 1111 1111 11. Bipolar Offset and Full-Scale Error Adjustment Bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. Again, bipolar offset error must be adjusted before full-scale error. Bipolar offset error adjustment is achieved by adjusting the offset applied to the AIN - input. For zero offset error apply - 125V (i.e., - 0.5LSB) at AIN+ and adjust the offset at the AIN- input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. For full-scale adjustment, an input voltage of 2.047625V (FS - 1.5LSBs) is applied to AIN+ and R2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11.
R8 100 ANALOG INPUT R1 50k
R7 48k 1 AIN
+
5V VDD R1 50k
R3 24k R5 R2 47k 50k
R4 100
2 3
AIN- VREF LTC1417
R6 24k 10F 0.1F
4 5
REFCOMP AGND V SS
1417 F06a
Figure 6a. Offset and Full-Scale Adjust Circuit If - 5V Is Not Available
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-5V ANALOG INPUT R3 24k R5 R2 47k 50k R6 24k 10F 0.1F R4 100 1 2 3 4 5 AIN+ AIN- VREF
5V VDD
LTC1417
REFCOMP AGND V SS
1417 F06b
-5V
Figure 6b. Offset and Full-Scale Adjust Circuit If - 5V Is Available
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LTC1417
BOARD LAYOUT AND GROUNDING To obtain the best performance from the LTC1417, a printed circuit board with ground plane is required. The ground plane under the ADC area should be as free of breaks and holes as possible, such that a low impedance path between all ADC grounds and all ADC decoupling capacitors is provided. It is critical to prevent digital noise from being coupled to the analog input, reference or analog power supply lines. Layout should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 5 (AGND) and Pin 10 (DGND) and all other analog grounds should be connected to this single analog ground plane. The REFCOMP bypass capacitor and the VDD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1417 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN- leads will be rejected by the input CMRR. The AIN- input can be used as a ground sense for the AIN+ input; the LTC1417 will hold and convert the difference voltage between AIN+ and AIN-. The leads to AIN+ (Pin 1) and AIN- (Pin 2) should be kept as short as possible. In applications where this is not possible, the AIN+ and AIN- traces should be run side by side to equalize coupling.
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AIN+ AIN- VREF 3 1F REFCOMP 4 10F 2
LTC1417 AGND 5 VSS 15 10F VDD 16 10F DGND 10
DIGITAL SYSTEM
ANALOG INPUT CIRCUITRY
+ -
ANALOG GROUND PLANE
1417 F07
Figure 7. Power Supply Grounding Practice
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LTC1417
APPLICATIONS INFORMATION
SUPPLY BYPASSING High quality, low series resistance ceramic, 10F bypass capacitors should be used at the VDD and REFCOMP pins. Surface mount ceramic capacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively 10F tantalum capacitors in parallel with 0.1F ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. DIGITAL INTERFACE The LTC1417 operates in serial mode. The RD control input is common to all peripheral memory interfacing. Only four digital interface lines are required, SCLK, CONVST, EXTCLKIN and DOUT. SCLK, the serial data shift clock can be an external input or supplied by the LTC1417 internal clock. Internal Clock The ADC has an internal clock. Either the internal clock or an external clock may be used as the conversion clock (see Figure 9). The internal clock is factory trimmed to achieve a typical conversion time of 1.8s and a maximum conversion time over the full operating temperature range of 2.5s. No external adjustments are required, and with the guaranteed maximum acquisition time of 0.5s, throughput performance of 400ksps is assured. Power Shutdown The LTC1417 provides two power shutdown modes, nap and sleep, to save power during inactive periods. The nap mode reduces the power by 80% and leaves only the digital logic and reference powered up. The wake-up time from nap to active is 500ns (see Figure 8). In sleep mode all bias currents are shut down and only leakage current remains-- about 2A. Wake-up time from sleep mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 30ms with the recommended 10F capacitor. Shutdown is controlled by Pin 11 (SHDN); the ADC is in shutdown when it is low. The shutdown mode is selected with Pin 12 (RD); low selects nap, high selects sleep.
SHDN t1 CONVST
1417 F08
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Figure 8. SHDN to CONVST Wake-Up Timing
Conversion Control Conversion start is controlled by the CONVST input. A falling edge of CONVST pin will start a conversion. Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. Data Output Output will be active when RD is low. A high RD will threestate the ouput. In unipolar mode (VSS = 0V) the data will be in straight binary format (corresponding to the unipolar input range). In bipolar mode (VSS = - 5V), the data will be in two's complement format (corresponding to the bipolar input range). Serial Output Mode Conversions are started by a falling CONVST edge. After a conversion is completed and the output shift register has been updated, BUSY will go high and valid data will be available on DOUT (Pin 9). This data can be clocked out either before the next conversion starts or it can be clocked out during the next conversion. To enable the serial data output buffer and shift clock, RD must be low.
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LTC1417
APPLICATIONS INFORMATION
Figure 9 shows a function block diagram of the LTC1417. There are two pieces to this circuitry: the conversion clock selection circuit (EXTCLKIN and CLKOUT) and the serial port (SCLK, DOUT and RD). Conversion Clock Selection In Figure 9, the conversion clock controls the internal ADC operation. The conversion clock can be either internal or external. By connecting EXTCLKIN high, the internal clock is selected. This clock generates 16 clock cycles which feed into the SAR for each conversion. To select an external conversion clock, apply an external conversion clock to EXTCLKIN (Pin 6). (When an external shift clock (SCLK) is used during a conversion, the SCLK should be used as the external conversion clock to avoid the noise generated by the asynchronous clocks. To maintain accuracy the external conversion clock frequency must be between 50kHz and 9MHz.) The SAR sends an end of conversion signal, EOC, that gates the external conversion clock so that only 16 clock cycles can go into the SAR, even if the external clock, EXTCLKIN, contains more than 16 cycles. When RD is low, these 16 cycles of conversion clock (whether internally or externally generated) will appear on CLKOUT during each conversion and then CLKOUT will remain low until the next conversion. If desired, CLKOUT can be used as a master clock to drive the serial port. Because CLKOUT is running during the conversion, it is important to avoid excessive loading that can cause large supply transients and create noise. For the best performance, limit CLKOUT loading to 20pF. Serial Port The serial port in Figure 9 is made up of a 16-bit shift register and a three-state output buffer that are controlled by two inputs: SCLK and RD. The serial port has one output, DOUT, that provides the serial output data. The SCLK is used to clock the shift register. Data may be clocked out with the internal conversion clock operating as a master by connecting CLKOUT (Pin 8) to SCLK (Pin 7) or with an external data clock applied to SCLK. The minimum number of SCLK cycles required to trans-
DATA IN 14
CLOCK INPUT SHIFT REGISTER
DATA OUT
SAR
16 CONVERSION CLOCK CYCLES THREE STATE BUFFER 8
EOC CLOCK DETECTOR INTERNAL CLOCK
Figure 9. Functional Block Diagram
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***
7 12
SCLK RD
THREE STATE BUFFER
9
DOUT
CLKOUT
***
6
EXTCLKIN
14
BUSY
1417 F09
LTC1417
APPLICATIONS INFORMATION
fer a data word is 14. Normally, SCLK contains 16 clock cycles for a word length of 16 bits; 14 bits with MSB first, followed by two trailing zeros. A logic high on RD disables SCLK and three-states DOUT. In case of using a continuous SCLK, RD can be controlled to limit the number of shift clocks to the desired number (i.e., 16 cycles) and to three-state DOUT after the data transfer. In power shutdown mode (SHDN = low), a high RD selects sleep mode while a low RD selects nap mode. DOUT outputs the serial data; 14 bits, MSB first, on the falling edge of each SCLK (see Figures 10 and 11). If 16 SCLKs are provided, the 14 data bits will be followed by two zeros. The MSB (D13) will be valid on the first rising and the first falling edge of the SCLK. D12 will be valid on
SCLK VIL t11 t12 DOUT
1417 F10
CONVST
13
CONVST
(SAMPLE N) EXTCLKIN = 5 CONVST t10 t3 BUSY (= RD) t7 1 CLKOUT (= SCLK) 2 3 4 5 6 7 8 9 10 11 12 13 HOLD t2
DOUT
Hi-Z
D13
D12
D11
D10
D9
D8
CLKOUT (= SCLK)
VIL t11 t12
DOUT
D13
Figure 11. Internal Conversion Clock Selected. Data Transferred During Conversion Using the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
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Figure 10. SCLK to DOUT Delay
the second rising and the second falling edge as will all the remaining bits. The data may be captured on either edge. The largest hold time margin is achieved if data is captured on the rising edge of SCLK. BUSY gives the end of conversion indication. When the LTC1417 is configured as a master serial device, BUSY can be used as a framing pulse and to three-state the serial port after transferring the serial output data by tying it to the RD pin.
BUSY RD SCLK
14 12 7
BUSY (= RD) P OR DSP (CONFIGURED AS SLAVE) OR SHIFT REGISTER
LTC1417 CLKOUT DOUT 8 9
CLKOUT ( = SCLK) DOUT
1417 F11a
(SAMPLE N + 1)
t5 SAMPLE HOLD
14
15
16
1
2
3
t4 D6 D5 D4 D3 D2 D1 D0 FILL ZEROS D13 Hi-Z D13 D12 DATA N t8
1417 F11b
D11
DATA (N - 1) tCONV
D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK
D11
VOH VOL
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LTC1417
APPLICATIONS INFORMATION
Figures 11 to 14 show several serial modes of operation, demonstrating the flexibility of the LTC1417 serial port. Serial Data Output During a Conversion Using Internal Conversion Clock for Conversion and Data Transfer. Figure 11 shows data from the previous conversion being clocked out during the conversion with the LTC1417 internal clock providing both the conversion clock and the SCLK. The internal clock has been optimized for the fastest conversion time, consequently this mode can provide the best overall speed performance. To select an internal conversion clock, tie EXTCLKIN (Pin 6) high. The internal clock appears on CLKOUT (Pin 8) which can be tied to SCLK (Pin 7) to supply the SCLK. Using External Clock for Conversion and Data Transfer. In Figure 12, data from the previous conversion is output during the conversion with an external clock providing both the conversion clock and the shift clock. To select an external conversion clock, apply the clock to EXTCLKIN. The same clock is also applied to SCLK to provide a data shift clock. To maintain accuracy the conversion clock frequency must be between 50kHz and 9MHz.
CONVST
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CONVST
(SAMPLE N) t2 CONVST t10 t3 BUSY (= RD) tdEXTCLKIN 1 EXTCLKIN (= SCLK) t7 DOUT Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FILL ZEROS t4 D13 Hi-Z D13 D12 DATA N t8 EXTCLKIN (= SCLK) tLEXTCLKIN VIL t11 t12 DOUT D13 D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK D11 VOH VOL tHEXTCLKIN
1417 F12b
2
3
4
5
6
Figure 12. External Conversion Clock Selected. Data Transferred During Conversion Using the External Clock (External Clock Drives Both EXTCLKIN and SCLK)
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BUSY RD
14 12 6
BUSY (= RD)
EXTCLKIN ( = SCLK) P OR DSP
EXTCLKIN LTC1417 SCLK DOUT 9
7 DOUT
1417 F12a
(SAMPLE N + 1)
t5 HOLD SAMPLE HOLD
7
8
9
10
11
12
13
14
15
16
1
2
3
D11
DATA (N - 1) tCONV
LTC1417
APPLICATIONS INFORMATION
It is not recommended to clock data with an external clock during a conversion that is running on an internal clock because the asynchronous clocks may create noise. Serial Data Output After a Conversion Using Internal Conversion Clock and External Data Clock. In this mode, data is output after the end of each conversion but before the next conversion is started (Figure 13). The internal clock is used as the conversion clock and an external clock is used for the SCLK. This mode is useful in applications where the processor acts as a master serial device. This mode is SPI and MICROWIRETM compatible. It also allows operation when the SCLK frequency is very low (less than 30kHz). To select the internal conversion clock tie EXTCLKIN high. The external SCLK is applied to SCLK. RD can be used to gate the external SCLK, such that data will clock only after RD goes low and to three-state DOUT after data transfer. If more than 16 SCLKs are provided, more zeros will be filled in after the data word indefinitely.
CONVST
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CONVST
EXTCLKIN = 5 CONVST
t2
t3 BUSY HOLD t6 RD 1 SCLK t7 DOUT (SAMPLE N) tCONV DATA N Hi-Z D13 12 11 10 9 8 7 2 3 4 5 6 7
Figure 13. Internal Conversion Clock Selected. Data Transferred After Conversion Using an External SCLK. BUSY Indicates End of Conversion
MICROWIRE is a trademark of National Semiconductor Corporation.
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BUSY RD SCLK
14 12 7
INT C0 SCK P OR DSP
LTC1417 DOUT 9
MISO
1417 F13a
t10 t5 SAMPLE t9
8
9 10 11 12 13 14 15 16
t8 6 5 4 3 2 1 0 FILL ZEROS Hi-Z
1417 F13b
SCLK VIL
t LSCLK t HSCLK t11 t12
DOUT
D13
D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK
D11
VOH VOL
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LTC1417
APPLICATIONS INFORMATION
Using External Conversion Clock and External Data Clock. In Figure 14, data is also output after each conversion is completed and before the next conversion is started. An external clock is used for the conversion clock and either another or the same external clock is used for the SCLK. This mode is identical to Figure 13 except that an external clock is used for the conversion. This mode allows the user to synchronize the A/D conversion to an external clock either to have precise control of the internal bit test timing or to provide a precise conversion time. As in
13 6 14 12
CONVST
CONVST EXTCLKIN BUSY RD LTC1417 SCLK DOUT 9
tdEXTCLKIN 1 EXTCLKIN t2 CONVST
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
t3 BUSY HOLD t6 RD 1 SCLK t7 DOUT (SAMPLE N) tCONV DATA N Hi-Z D13 12 11 10 9 8 7 2 3 4 5 6 7
Figure 14. External Conversion Clock Selected. Data Transferred After Conversion Using an External SCLK. BUSY Indicates End of Conversion
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Figure 13, this mode works when the SCLK frequency is very low (less than 30kHz). However, the external conversion clock must be between 30kHz and 9MHz to maintain accuracy. If more than 16 SCLKs are provided, more zeros will be filled in after the data word indefinitely. To select the external conversion clock, apply an external conversion clock to EXTCLKIN. The external SCLK is applied to SCLK. RD can be used to gate the external SCLK such that data will clock only after RD goes low.
CLKOUT INT C0 P OR DSP
7
SCK MISO
1417 F14a
1
2
3
4
t4
t10 t5 SAMPLE t9
8
9 10 11 12 13 14 15 16
t8 6 5 4 3 2 1 0 FILL ZEROS Hi-Z
1417 F14b
SCLK VIL
t LSCLK t HSCLK t11 t12
DOUT
D13
D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK
D11
VOH VOL
LTC1417
PACKAGE DESCRIPTIO U
Dimensions in inches (millimeters) unless otherwise noted.
GN Package 16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
0.009 (0.229) REF
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1 0.015 0.004 x 45 (0.38 0.10) 0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727)
23
4
56
7
8 0.004 - 0.0098 (0.102 - 0.249)
0.008 - 0.012 (0.203 - 0.305)
0.025 (0.635) BSC
GN16 (SSOP) 0398
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LTC1417
TYPICAL APPLICATIO
Single 5V Supply, 400kHz, 14-Bit Sampling A/D Converter
5V DIFFERENTIAL ANALOG INPUT (0V TO 4.096V) VREF OUTPUT 2.5V 1F 10F 1 2 3 4 5 6 P CONTROL LINES 7 8 AIN+ AIN- VREF REFCOMP AGND EXTCLKIN SCLK CLKOUT VDD VSS BUSY CONVST RD SHDN DGND DOUT
1417 TA03
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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16 15 14 13 12 11 10 9 P CONTROL LINES 10F LTC1417
1417i LT/TP 0199 4K * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 1999

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